Device isolation techniques play an important role in the design and performance of highly integrated semiconductor circuits by electrically isolating regions and devices therein from adjacent devices and regions. Such integrated semiconductor circuits included memory devices having arrays of memory cells and peripheral devices for driving the memory cells, for example. Moreover, as the degree of integration in semiconductor circuits increases, there is a concomitant need to develop techniques for forming isolation regions which can be scaled to provide isolation regions having smaller dimensions, but without sacrificing the isolation capability of the regions.
Attempts to improve the isolation capability of field oxide regions in a semiconductor substrate by making these regions narrower to facilitate higher levels of lateral integration, while at the same time thicker to compensate for the decrease in isolation capability caused by the reduction in separation distance between adjacent devices, pose significant drawbacks. In particular, the formation of isolation regions of increased thickness typically causes an increase in the nonuniformity of subsequently formed regions and layers (e.g., metal wiring) which cover both the active regions and inactive isolation regions. Unfortunately, such nonuniformities, which may be characterized by a vertical "step-height" between the face of the semiconductor substrate where an active region(s) is formed and the top surface of the isolation regions, typically cause a reduction in yield as higher and higher levels of integration are attempted.
One typical method for forming electrical isolation regions in semiconductor substrates is referred to as a local oxidation of silicon (LOCOS) method. For example, referring to FIGS. 1-2, a method of forming an electrical isolation region 13 in a semiconductor substrate 1 using LOCOS, is illustrated. In particular, FIG. 1 illustrates a structure resulting from the steps of forming, in sequence, a pad oxide film 3 and a silicon nitride film 5 on a silicon substrate 1. The silicon nitride film 5 is then patterned by selectively etching the film to define openings 9 therein, which extend opposite those portions of the substrate wherein inactive/isolation regions are to be formed. The remaining portions 11 of the silicon nitride film 5 are also defined during the etching step, opposite those portions of the substrate wherein active/device regions are to be formed. Referring still to FIG. 1, preliminary channel-stop impurity regions 7 are then formed in the inactive portions of the substrate by implanting dopants into the substrate, using the patterned silicon nitride film 5 as a mask.
Referring now to FIG. 2, a thermal oxidation step is performed to form field oxide isolation regions 13, using the patterned silicon nitride film 5 as an oxidation mask. During this oxidation step, diffusion of the implanted dopants also takes place to form channel-stop impurity regions 15. As will be understood by those skilled in the art, during the thermal oxidation step, bird's beak shaped oxide extensions will form underneath the patterned silicon nitride film 5, as illustrated. The formation of bird's beak extensions causes the effective width of the field oxide isolation regions to increase, as represented by numerals 17 and 20. Here, reference numeral 19 illustrates the increase in width on each side of the field oxide isolation region 13 which is attributable to the bird's beak shaped extensions. Finally, reference numeral 23 represents the actual size of an active region, which is reduced by the bird's beak shaped extensions. Accordingly, the LOCOS method may not be suitable for applications requiring high degrees of integration, because the lateral width of the bird's beak extensions is not readily scalable. This is particularly true when thicker isolation regions are used to increase isolation capability, because thicker isolation regions typically cause an increase in the lateral dimension of the bird's beak extensions.
FIGS. 3-6 also illustrate a conventional method of forming shallow trench isolation (STI) regions in a semiconductor substrate 21. In particular, as illustrated by FIG. 3, a pad oxide film 22 having a thickness of about 240 .ANG. is formed on the substrate 21 by thermal oxidation. Then, a silicon nitride film 24, having a thickness of about 1500 .ANG., is formed on the pad oxide film 22 by a low pressure chemical vapor deposition method (LPCVD). An oxide mask 26 is then formed by depositing an oxide film having a thickness of about 1000 .ANG. and then patterning the oxide film using conventional etching techniques. Referring to FIG. 4, trenches are then formed in the substrate 21 by reactive ion etching (RIE) the silicon nitride film 24 and the pad oxide film 22, using the oxide mask 26, and then dry-etching the substrate 21, as will be understood by those skilled in the art. The trenches may be made of varying width, depending on the application and degree of isolation required. The exposed silicon on the sidewalls and bottom of the trenches is then thermally oxidized to form an oxide film 27. Referring still to FIG. 4, a polycrystalline silicon film having a thickness of approximately 5000 .ANG. or thicker is then deposited into the trenches and anisotropically etched to form a polycrystalline silicon film 28. As illustrated, the relatively narrow trench is typically completely filled by the polycrystalline silicon film 28, however the film 28 in the wider trench may be concave in shape and thereby have a centrally depressed region at the middle of the trench. Accordingly, the profile of the silicon film 28 may vary depending on the width, depth and shape of the trench.
Referring now to FIG. 5, the polycrystalline silicon film 28 is then thermally oxidized to form a field oxide film 29, however, the concave profile of the polycrystalline silicon film 28 is typically replicated in the profile of the field oxide film 29. Then, as illustrated by FIG. 6, the oxide mask 26, the silicon nitride film 24 and the pad oxide film 22 are removed, preferably by a wet-etch technique using a buffered oxide etchant (BOE) and a phosphoric acid solution. A sacrificial oxide film (not shown) is then grown and etched to form the resulting trench isolation structure. Unfortunately, the central depression G in the field oxide film 29 increases the roughness of upper level surfaces and may reduce the yield of integrated circuits formed in the substrate by, among other things, causing shorts between metal lines such as gate and bit lines of an integrated memory device. In addition, as illustrated by reference R, bird's beak shaped extensions may also be present which, as described above with respect to FIGS. 1-2, can cause an increase in the effective lateral width of the trench isolation regions. Furthermore, the step of removing the oxide mask 26 typically results in a removal of a portion of the field oxide film 29 as well. Accordingly, the thickness of the field oxide film 29 may have to be made greater to account for the partial removal during the step of removing the oxide mask 26. Yet, by increasing the thickness of the field oxide film 29, the lateral width of the bird's beak extensions also increases and thereby further inhibits attempts to increase integration densities. This and other deficiencies of LOCOS and STI isolation techniques are more fully described in U.S. Pat. Nos. 5,385,861 to Bashir et al., 5,492,858 to Bose et al. and 5,494,857 to Cooperman et al.
In order to improve upon the above-mentioned trench isolation method, chemical-mechanical polishing techniques (CMP) have been proposed. Such polishing techniques typically include the step of polishing the surface of the substrate to remove excess field insulation, after the trenches have been formed and filled with an appropriate insulation material. However, a dishing phenomenon, known to those skilled in the art, may occur when trench isolation regions of substantial width are formed. This phenomenon, which is described in the aforementioned U.S. Pat. No. 5,494,857 to Cooperman et al., typically causes poor local planarization and can therefore reduce yield. Attempts to reduce the occurrence of the dishing phenomenon are described in an article by B. Davari et al., entitled A New Planarization Technique, Using a Combination of RIE and Chemical Mechanical Polish (CMP), IEDM Technical Digest, pp. 61-64 (1989) and the aforementioned U.S. Pat. No. 5,494,857 to Cooperman et al. In this article, a combination of RIE and CMP steps are performed to improve planarization. In particular, an initial planarization step using RIE is performed prior to a final planarization step using CMP, in order to reduce the degree of dishing present in the resulting structure, as described with respect to FIG. 5 of the aforementioned Davari article. Unfortunately, in addition to requiring a separate RIE step, this method may require additional steps such as a step of forming block resist patterns over relatively wide isolation regions, in order to improve the degree of planarization that can be achieved.
Thus, notwithstanding the above described methods, there continues to be a need for relatively simple methods of forming isolation regions having uniformly planar surfaces, which can be scaled to allow for high levels of integration.